With the development of electronic technology, the dimension of electronic device is getting smaller and more compact. To save space and increase transmission speed, the serial transmission technology is in wide spread use. For example, the loader of the DVD-ROM or CD-ROM transfers signals serially. In such a serial transmission, a clock is recovered from the received data. Only when the correct clock is enssured, the receiver can sample the received data correctly.
Referring to FIG. 1A, a conventional clock recovery circuit is illustrated. When the phase of a clock signal is lagged to the phase of DATA signal, the phase detector 91 outputs a frequency increasing signal (UP signal) for activating a current source 92 and charging a capacitor 93. The voltage VCOin of the capacitor 93 will be increased due to charging of the capacitor 93. When the voltage VCOin is increased, the frequency of the output signals of a voltage-controlled oscillator 94 will be increased for compensating the lag phase of the clock CK. When the phase of the clock signal CK is leading the phase of the data signal DATA, the phase detector 91 outputs a frequency decreasing signal (DN signal) for driving a current source 95 and the capacitor 93 will be discharged. The voltage VCOin of the capacitor 93 will be decreased due to the discharge. After the voltage VCOin is decreased, the frequency of the output signal of the voltage-controlled oscillator 94 is also decreased so that the phase of the clock signal CK is lagged to be in-phase with the data signal DATA.
FIGS. 1B and 1C show the circuit and time sequence of the phase detector 91 of the clock recovery circuit. In FIG. 1C, arrow A represents that the clock signal CK and data signal DATA are in phase, arrow B represents that phase of the signal CK is lagged of the data signal DATA, and arrow C represents that phase of the signal CK is led of the data signal DATA. When the clock signal CK is in-phase with the data signal DATA, the voltage VCOin still exists, as indicated by arrow D in FIG 1C. This will cause jitter in the clock signal and meanwhile, the voltage VCOin generates a DC offset so that the phase of the clock CK has offset with respect to the phase of the data signal DATA.
FIGS. 2A and 2B show the improved circuit and time sequence of the clock recovery circuit for solving the aforementioned problem. As shown in the FIG. 2B, the phase detector 91 can eliminate the DC offset of the voltage VCOin, while as indicating by arrow D of FIG. 2B, it is found that the clock still has jitters.
Therefore, it is desirable to provide an improved phase detector with jitter-less for a clock recovery circuit to mitigate and/or obviate the aforementioned problems.